MOSFET Grid Example: Difference between revisions
(Created page with "= MOSFET Grid Example = line x loc=-0.05 spac=0.01 tag=TopOx line x loc=0.03 spac=0.001 tag=TopSi line x loc=0.04 spac=0.0025 line x loc=0.06 spac=0.01 l...") |
|||
| Line 11: | Line 11: | ||
line x loc=3.00 spac=0.1 tag=Bottom | line x loc=3.00 spac=0.1 tag=Bottom | ||
This section specifies the vertical grid spacings and [[lineCommand | line]] positions. The first line is placed at a position of -0.05um, and is tagged "TopOx". The second line is given a spacing of 10Å and is tagged "TopSi". It is placed at 0.03um. The next lines help control the grid spacing as we go deeper into the silicon. As a rule of thumb, grid should be fine in device simulation in regions with charge. So the grid is fine for the inversion layer and at the bottom of the source and drain junctions. The final line is placed at 3.0um and tagged "Bottom". This line is at a depth deep enough to accommodate the depletion layers. | |||
line y loc=0.00 spac=0.05 tag=Left | |||
line y loc=0.10 spac=0.01 | |||
line y loc=0.15 spac=0.01 | |||
line y loc=0.25 spac=0.007 tag=GLE | |||
line y loc=0.35 spac=0.05 | |||
line y loc=1.25 spac=0.1 | |||
line y loc=2.15 spac=0.05 | |||
line y loc=2.25 spac=0.007 tag=GRE | |||
line y loc=2.35 spac=0.01 | |||
line y loc=2.40 spac=0.01 | |||
line y loc=2.50 spac=0.05 tag=Right | |||
This section | This section defines the grid laterally from source to drain of the device. This will be a 2.0um wide Gate, as indicated by the tags GLE and GRE. Spacings are kept fine near the edge of the gate, but get wider in the middle where the behavior of the device is more one-dimensional. | ||
region Oxide xlo=TopOx xhi=TopSi ylo=GLE yhi=GRE | |||
region Silicon xlo=TopSi xhi=Bottom ylo=Left yhi=Right | |||
The previous | The previous two lines define a large block of silicon and an oxide layer that stretches over the top section where the gate is located. | ||
init | init | ||
Finally, the information is used to create a grid for simulation. | |||
Latest revision as of 19:32, 4 June 2020
MOSFET Grid Example
line x loc=-0.05 spac=0.01 tag=TopOx line x loc=0.03 spac=0.001 tag=TopSi line x loc=0.04 spac=0.0025 line x loc=0.06 spac=0.01 line x loc=0.09 spac=0.005 line x loc=0.10 spac=0.01 line x loc=0.12 spac=0.025 line x loc=0.19 spac=0.05 line x loc=3.00 spac=0.1 tag=Bottom
This section specifies the vertical grid spacings and line positions. The first line is placed at a position of -0.05um, and is tagged "TopOx". The second line is given a spacing of 10Å and is tagged "TopSi". It is placed at 0.03um. The next lines help control the grid spacing as we go deeper into the silicon. As a rule of thumb, grid should be fine in device simulation in regions with charge. So the grid is fine for the inversion layer and at the bottom of the source and drain junctions. The final line is placed at 3.0um and tagged "Bottom". This line is at a depth deep enough to accommodate the depletion layers.
line y loc=0.00 spac=0.05 tag=Left line y loc=0.10 spac=0.01 line y loc=0.15 spac=0.01 line y loc=0.25 spac=0.007 tag=GLE line y loc=0.35 spac=0.05 line y loc=1.25 spac=0.1 line y loc=2.15 spac=0.05 line y loc=2.25 spac=0.007 tag=GRE line y loc=2.35 spac=0.01 line y loc=2.40 spac=0.01 line y loc=2.50 spac=0.05 tag=Right
This section defines the grid laterally from source to drain of the device. This will be a 2.0um wide Gate, as indicated by the tags GLE and GRE. Spacings are kept fine near the edge of the gate, but get wider in the middle where the behavior of the device is more one-dimensional.
region Oxide xlo=TopOx xhi=TopSi ylo=GLE yhi=GRE region Silicon xlo=TopSi xhi=Bottom ylo=Left yhi=Right
The previous two lines define a large block of silicon and an oxide layer that stretches over the top section where the gate is located.
init
Finally, the information is used to create a grid for simulation.